1. Field of the Invention
This invention relates to a method of manufacturing semiconductor integrated circuits, and more particularly to a process for shallow trench isolation formation to achieve high device performance.
2. Background of the Invention
Semiconductor integrated circuit devices typically comprise silicon and multiple layers of vertically stacked metal interconnect layers with dielectric materials disposed between them. The fabrication of such devices typically involves the repeated deposition or growth, patterning, and etching of thin films of semiconductor, metal, and dielectric materials.
Isolation structures are commonly implemented in semiconductor manufacturing to electrically isolate circuit components from one another. Structures formed by the local oxidation of silicon (LOCOS) are effective but tend to produce a bird's beak structure profile which reduces available silicon estate. To reduce the silicon estate loss trench isolation may be implemented. Trenches, typically cut by a plasma etch, have more vertical walls than isolation structures formed by the LOCOS method, and are therefore, preferred for some applications. Generally, isolation structures comprise an oxide formed between diffused active regions of adjacent semiconductor components creating a barrier that prevents current flowing through one component from leaking into neighboring components.
The number of circuit components which can be included on a silicon substrate is limited by the size of the components and the available surface area of the silicon substrate. The active surface area is maximized by minimizing the isolation regions of the substrate. LOCOS isolation structures work well for components with dimensions greater than about one micron, but are not adequately suited for components with dimensions less than one micron.
Shallow trench isolation, or STI, structures have been developed for utilization in semiconductor devices with sub-micron dimensions. STI structures are typically defined within the substrate, rather than grown over the surface as with field oxide regions.
A prior art STI structure is shown in FIG. 1. Trench 1 is etched into substrate 2 between a pair of difflusion regions 3 and oxidation is performed at atmospheric pressure in dry oxygen at a temperature of about 900-1100.degree. C. to form an oxide layer 5. High pressure techniques are typically used to form thick oxides which are generally oxides having a thickness greater than about 500 .ANG.. Oxide layer 5 generally varies in thickness due, at least in part, to damage caused by plasma etching. A thermal oxidation step recovers damage on the side wall and bottom of the trench and reduces leakage. A silicon dioxide material 4 is deposited into trench 1 to substantially fill trench 1. Excess silicon dioxide material 4 remaining on the surface of substrate 2 is removed by chemical mechanical polishing of the surface, which results in a planarized surface. As shown in FIG. 1 a (an enlarged view of a portion of FIG. 1) the resulting trench 1 has facet formation 13 at the bottom corners. Trench 1 also has sharp edges 14 at the top corners as shown in FIG. 1b (an enlarged view of FIG. 1) and may have a bow-shaped side wall 7 as depicted in FIG. 1. The side wall bowing is mainly caused by plasma etching damage during trench formation and the following oxidation step. This occurs because damaged side walls oxidize faster than undamaged areas. The sharp edges 14 may be formed due to stress at the corners and a low oxygen diffusion coefficient.
Sharp edges 14 may diminish the structural integrity of substrate 2. Consequently, when subsequent layers are deposited over and into trench 1, dislocations in the silicon crystal are generated near and around sharp edges 14. Dislocations usually migrate deeper into lower portions of the substrate during subsequent thermal processing steps, such as annealing. As dislocations 6 migrate away from sharp edges 14, dislocations 6 form convenient paths for leakage currents. As a result, dislocations 6 can have the detrimental effect of providing an electrical conduction bridge that allows current flowing through one device to leak into an adjacent device.
In further processing, a dielectric layer 8 is typically deposited over the planarized surface. A conductive pattern 10 is then deposited over dielectric layer 8. The conductive pattern 10 may be polished polycrystalized silicon/tungsten silicide stacked materials. Sharp edges 14 tend to intensify the electric fields in dielectric layer 8, which causes bunching of electric field 12. The locally enhanced electric field 12 has a disadvantageous effect of dominating on-currents in transistor gates. As a result, transistor performance suffers because the transistor will tend to switch on at voltages lower than originally designed. The bunching of electric field 12 underlying sharp edges 14 also may adversely impact the integrity of dielectric layer 8. Consequently, dielectric layer 8 may break down at lower voltages or after less time.
A rounded corner at the mouth of the trench has been used to reduce silicon structure dislocations caused by subsequent depositions and to reduce the intensity of the electric fields generated over the STI structure and the leakage currents between isolated adjacent devices. The curved profile is made by anisotropically etching a blanket of silicon over a mask on the substrate to form temporary spacers having curved profiles at the side walls of an aperture. The temporary spacers transfer the curved profiles to a mouth of a shallow trench being etched at the region of the substrate as the temporary spacers are etched away. However, this method does not address dislocations at the bottom corners of the trench.
Another problem which negatively affects the electrical integrity of a semiconductor device is p.sup.+ substrate up-diffusion. When a p.sup.- epitaxial silicon layer is on top of a p.sup.+ layer, there is dopant diffusion up from the p.sup.+ layer to the p.sup.- layer adversely affecting device performance. Up diffusion is more significant at higher temperatures and with thinner p.sup.- epitaxial layers. By reducing the thermal budget during device fabrication, up-diffusion may be minimnized.
Conventional STI formation methods may lead to the formation of sharp corners in the trench, which lead to leakage and device breakdown. Therefore, It is desirable to have a process for STI formation that achieves low thermal budget, better corner rounding, reduced leakage current, and suppressed p.sup.+ substrate up-diffusion.